Publications

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. In ASP-DAC.

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang (2024). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In ASP-DAC.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (2024). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. In ASP-DAC.

Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie (2024). OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited). In ICCAD.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2024). Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. In TCAD.

Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie (2024). RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. In ISLAD.

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. In DAC.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2023). MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In ICCAD.

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Wenji Fang, Guangyu Hu, Hongce Zhang (2023). r-map: Relating Implementation and Specification in Hardware Refinement Checking. In TCAD.

Wenji Fang, Hongce Zhang (2023). WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. In TACAS.

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