Publications

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. In DAC.

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2023). MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In ICCAD.

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Wenji Fang, Guangyu Hu, Hongce Zhang (2023). r-map: Relating Implementation and Specification in Hardware Refinement Checking. In TCAD.

Wenji Fang, Hongce Zhang (2023). WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. In TACAS.

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