Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL StageJan 15, 2025·Shang LiuWenji Fang,Yao Lu,Qijun Zhang,Zhiyao Xie· 0 min read PDF CiteTypeConference paperPublicationIn Asia and South Pacific Design Automation Conference (ASP-DAC)Last updated on Apr 4, 2025 AuthorsWenji FangPhD Student ← AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs Jan 15, 2025SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model Jan 10, 2025 →
