Wenji Fang
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    • A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA
    • NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
    • ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
    • SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits
    • CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
    • Profile-Guided Temporal Prefetching
    • A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
    • AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
    • Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage
    • SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
    • RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
    • Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
    • Large circuit models: opportunities and challenges
    • OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)
    • Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
    • RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
    • MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
    • r-map: Relating Implementation and Specification in Hardware Refinement Checking
    • WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification
    • An Integrated Single-Shot Spectrometer With Large Bandwidth-Resolution Ratio and Wide Operation Temperature Range
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CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Jan 22, 2025·
Wenji Fang
Wenji Fang
,
Shang Liu
,
Jing Wang
,
Zhiyao Xie
· 0 min read
PDF Cite Code Poster Slides
Type
Conference paper
Publication
In International Conference on Learning Representations (ICLR)
Last updated on Apr 14, 2025
Wenji Fang
Authors
Wenji Fang
PhD Student
← SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits Feb 14, 2025
Profile-Guided Temporal Prefetching Jan 20, 2025 →

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