RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique

Jan 1, 2025·
Shang Liu
Wenji Fang
Wenji Fang
,
Yao Lu
,
Jing Wang
,
Qijun Zhang
,
Hongce Zhang
,
Zhiyao Xie
· 1 min read
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publication

The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. However, most existing approaches heavily rely on commercial LLMs such as ChatGPT, while open-source LLMs tailored for this specific design generation task exhibit notably inferior performance. The absence of high-quality open-source solutions restricts the flexibility and data privacy of this emerging technique. In this study, we present a new customized LLM solution with a modest parameter count of only 7B, achieving better performance than GPT-3.5 on all representative benchmarks for RTL code generation. Especially, it outperforms GPT-4 in VerilogEval Machine benchmark. This remarkable balance between accuracy and efficiency is made possible by leveraging our new RTL code dataset and a customized LLM algorithm, both of which have been made fully open-source. Furthermore, we have successfully quantized our LLM to 4-bit with a total size of 4GB, enabling it to function on a single laptop with only slight performance degradation. This efficiency allows the RTL generator to serve as a local assistant for engineers, ensuring all design privacy concerns are addressed.

Wenji Fang
Authors
PhD Candidate

Hi! I’m Wenji Fang (方闻绩), a Ph.D. candidate at the Electronic and Computer Engineering Department of the Hong Kong University of Science and Technology, advised by Prof. Zhiyao Xie. Previously, I received my M.Phil in microelectronics from the Hong Kong University of Science and Technology (Guangzhou), advised by Prof. Hongce Zhang & Prof. Zhiyao Xie, and my B.Eng in electrical engineering from Nanjing University of Aeronautics and Astronautics.

My research focuses on AI for Electronic Design Automation (EDA), with the goal of advancing AI-driven paradigms for VLSI design and verification. I have published 10+ first-author papers in leading EDA and AI venues, including DAC, ICCAD, ASP-DAC, TCAD, and ICLR.

I received the inaugural LLM-Aided Design Fellowship and the 2nd Place Award in the ACM SIGDA Student Research Competition. Beyond academia, I have gained industry experience through my internship at NVIDIA Research and Peng Cheng Laboratory.