Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
In modern VLSI design flow, evaluating the quality of register-transfer level (RTL) designs involves time-consuming logic synthesis using EDA tools, a process that often slows down …
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. …
shang-liu
Large circuit models: opportunities and challenges
Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than …
lei-chen
r-map: Relating Implementation and Specification in Hardware Refinement Checking
Refinement checking is an important formal verification method that checks if a hardware implementation complies with (in other words, refines) a given specification. It has been …
An Integrated Single-Shot Spectrometer With Large Bandwidth-Resolution Ratio and Wide Operation Temperature Range
There has been a rapidly growing demand for low-cost, integrated single-shot spectrometers to be embedded in portable intelligent devices. Even though significant progress has been …
ang-li
An example journal article
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