Paper-Conference

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

ziyan-guo

• Apr 1, 2026 • 1 min read

LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power

wenkai-li

• Apr 1, 2026 • 1 min read

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

yao-lu

• Apr 1, 2026 • 1 min read

SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models

shang-liu

• Sep 1, 2025 • 1 min read

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Wenji Fang

• Jun 30, 2025 • 1 min read

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Wenji Fang

• Mar 29, 2025 • 1 min read

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph

Wenji Fang

• Feb 15, 2025 • 1 min read

SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

shang-liu

• Feb 14, 2025 • 1 min read

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

wenkai-li

• Feb 14, 2025 • 1 min read

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design

Wenji Fang

• Jan 22, 2025 • 1 min read