Paper-Conference

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

Wenji Fang

• Jun 30, 2026 • 1 min read

E-Layout: Layout-Stage Restructuring via RL-Optimized Equality-Saturated Graph Retrieval-Augmented Generation

Wenji Fang

• Jun 29, 2026 • 1 min read

AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications

yuchao-wu

• Jun 28, 2026 • 1 min read

CorrectRTL: Boost RTL Generation Quality Through Automated Self-Correction with Instruction Decomposition

jing-wang

• Jun 27, 2026 • 1 min read

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA

Wenji Fang

• Jun 21, 2026 • 1 min read

RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

ziyan-guo

• Apr 1, 2026 • 1 min read

LEAP: A Self-Supervised Per-Cycle Toggle Propagation Model Supports Fast, Transferable, and Early Analysis of Layout Power

wenkai-li

• Apr 1, 2026 • 1 min read

COOL: A Cooling-Aware Point Transformer Framework for Thermal Prediction in Advanced 3D/3.5D IC Packaging

yao-lu

• Apr 1, 2026 • 1 min read

SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models

shang-liu

• Sep 1, 2025 • 1 min read

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment

Wenji Fang

• Jun 30, 2025 • 1 min read