Paper-Conference

Profile-Guided Temporal Prefetching

mengming-li

• Jan 20, 2025 • 1 min read

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage

shang-liu

• Jan 15, 2025 • 1 min read

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

zhiyuan-yan

• Jan 15, 2025 • 1 min read

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks

Wenji Fang

• Jan 15, 2025 • 1 min read

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

mengming-li

• Jan 10, 2025 • 1 min read

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited)

shang-liu

• Jul 21, 2024 • 1 min read

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

shang-liu

• Feb 1, 2024 • 1 min read

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Wenji Fang

• Feb 1, 2024 • 1 min read

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Pre-Synthesis PPA Estimation

Wenji Fang

• Jul 21, 2023 • 1 min read

Formal Verification

WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification

Wenji Fang

• Apr 22, 2023 • 1 min read