Paper-Conference

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Wenji Fang

• Feb 1, 2024 • 1 min read

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MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Pre-Synthesis PPA Estimation

Wenji Fang

• Jul 21, 2023 • 1 min read

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WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification

Wenji Fang

• Apr 22, 2023 • 1 min read

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An example conference paper

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Wenji Fang

• Jul 1, 2013 • 1 min read

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