Wenji Fang

Phd Student @ ECE HKUST

Hong Kong University of Science and Technology

Biography

Hi! I’m Wenji Fang (方闻绩), a Ph.D. student at the Electronic and Computer Engineering Department of the Hong Kong University of Science and Technology, advised by Prof. Zhiyao Xie. Previously, I received my M.Phil from the Hong Kong University of Science and Technology (Guangzhou), advised by Prof. Hongce Zhang, and my B.Eng from Nanjing University of Aeronautics and Astronautics.

Download my CV/resumé.

Interests

VLSI Design Quality Modeling
Hardware Formal Verification
AI for EDA

Education

Ph.D. in Electronic and Computer Engineering, starting from 2024
Hong Kong University of Science and Technology
M.Phil. in Microelectronics, 2024
Hong Kong University of Science and Technology (Guangzhou)
B.Eng in Electrical Engineering and Automation, 2021
Nanjing University of Aeronautics and Astronautics

Work Experience

Research Assistant

HKUST(GZ)

Dec 2021 – Jul 2022 Guangzhou, Guangdong, China

Responsibilities include:

Achieve an end-to-end unbounded formal verification framework for microprocessors
Employ symbolic simulation technique to model the microprocessor
Verify the functional correctness properties
Test the framework with multiple pipelined processor test cases

VLSI Physical Design Intern (“One Student One Chip” Project)

Peng Cheng Laboratory

Jul 2021 – Dec 2021 Shenzhen, Guangdong, China

Responsibilities include:

Complete an entire physical design process of an SoC
Participate in defining clock specification, design constriants
Design a single-cycle RISC-V processor

Publications

Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. In ASP-DAC.

Cite

Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang (2024). AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. In ASP-DAC.

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Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (2024). Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. In ASP-DAC.

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Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie (2024). OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation (Invited). In ICCAD.

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Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2024). Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. In TCAD.

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Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie (2024). RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. In ISLAD.

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Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie (2024). Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. In DAC.

Cite Project

Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie (2023). MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. In ICCAD.

PDF Cite Project Poster Slides

Wenji Fang, Guangyu Hu, Hongce Zhang (2023). r-map: Relating Implementation and Specification in Hardware Refinement Checking. In TCAD.

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Wenji Fang, Hongce Zhang (2023). WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification. In TACAS.

PDF Cite Project Slides Video